By R.K. Willardson and Albert C. Beer (Eds.)
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Additional resources for Applications and Devices Part B
The thin line is for the impurity profile. ’~) of excess holes at the left edge and excess electrons at the right edge, the field profile has a saddle in the middle and voltage is lowered below the value at breakdown. The situation is similar to that in dc condition shown in Fig. 7a. After the current has peaked, the voltage drops down ; generated carriers disappear in the time interval comparable to the carrier transit time. As is seen from Fig. 31, the current flows during a very small fraction of one cycle.
A p'nvn' v n+ Read diode. 17. Equivalent circuit of Read diode. Tildes indicate vectors. charge-layer width and obtained the following expression for the admittance20a: 0 2Y Y ( 0 )= u! 1 - e - j o - j 2 y ’ Y - - ( lww -)b), o2 2 The small-signal admittance calculated from the above expression reproduces most of the behavior of the exact admittance obtained from the numerical analysis shown in Figs. 10 and 11. A major qualitative difference between Read’s approximation and the exact analysis is the fact that in the former both real and imaginary parts of the admittance change sign at a single frequency o,,while in the exact analysis the real part changes sign at lower frequency than the imaginary part.
As the voltage approaches the peak, carriers start to be generated. Figures 32 and 33 show carrier distributions and field profile at several instants when the current goes through the peak. Numbers attached to the curves are times in picoseconds with respect to the moment when the current peaks. At 11 psec before the current peak, the current has just started to flow. The carriers are generated mostly at the right end of the space-charge region, where, although the field is lower than at the left end, more electrons, which have a larger ionization rate, are available.
Applications and Devices Part B by R.K. Willardson and Albert C. Beer (Eds.)